The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly, to a semiconductor device that may relieve hot electron induced punchthrough phenomenon even without using a gate tab, and a fabricating method thereof.
Recently, as a design rule of a semiconductor device shrinks to 100 nm or less, an interval between the source and the drain of a transistor narrows and the doping concentrations of the channel, source, and drain increase. Therefore, a phenomena such as a short channel effect (SCE), a hot carrier effect (HCE), and a gate induced drain leakage (GIDL) occur to reduce the electrical characteristics of a transistor.
Particularly, in the case of a positive metal oxide semiconductor (PMOS) transistor formed in a peripheral region, electrons are additionally generated by holes, which are majority carriers. These electrons are trapped into an isolation layer adjacent to an inversion channel of the PMOS transistor, leading to reduction of an effective channel length. The channel inversion caused by trapping of electrons is generated at the edge of an active region contacting a portion of the isolation layer under a gate pattern.
As described above, the undesired channel inversion in the PMOS transistor increases a leakage current during a turn-off operation to increase power consumption, reducing an operating speed, and reducing a breakdown voltage (BV). A phenomenon generating these limitations is generally called a hot electron induced punchthrough (HEIP) phenomenon.
To solve the limitations caused by the HEIP, a technology has been proposed which installs a gate tap at a point where HEIP phenomenon is induced, that is, a boundary region between an active region and an isolation region that overlaps a gate pattern in an aspect of the structure of a semiconductor device.
FIG. 1 illustrates a plan view of a typical semiconductor device having a gate tap.
Referring to FIG. 1, a gate tap 14 is formed at a gate electrode 13 located at the edge of an active region 12 to increase the length of this portion of the gate electrode 13. Therefore, the length W2 of a channel formed at the edge of the active region 12 contacting an isolation region 11 becomes longer than the length W1 of the channel formed at the active region 12, so that the HEIP phenomenon may be relieved.
However, as a channel length reduces as a semiconductor device becomes highly integrated, the length of the gate tap 14 needs to be increased to compensate for the reduced channel length. In this case, the active region 12 needs to be increased to maintain a constant interval between gate electrodes 13 in a region where transistors requiring the gate tap 14 are densely aggregated. This increases a net die size of a semiconductor device. Accordingly, it is difficult to improve the degree of integration of a semiconductor device. Also, when the degree of integration increases, the characteristic of a transistor is difficult to secure.